The invention relates to a charge-coupled device of the n-phase- one-electrode/bit or ripple phase type having a variable storage capacity comprising a semiconductor body having a charge transport channel defined at or near a surface of the semiconductor body and a system of clock electrodes on the surface, which can be connected to clock voltage means such that in a row of n successive electrodes an adjustable number of adjacent storage sites in which information is stored and which alternate with empty sites in which no information is stored can be induced.
Such a device is known inter alia from the European Patent Application No. 0099931 laid open to public inspection.
The invention is more particularly, but not exclusively of importance for memory devices having an SPS (Series/Parallel/Series) configuration. Such memories may advantageously be used, for example, for storing television pictures, in which event the information is introduced in series and after a given storage time must be read out again in series, as is described inter alia in the article "A digital field memory television reciever" by M. J. M. Pelgrom et al in I.E.E.E. Transactions on Consumer Electronics, Vol. CE-29, No. 3, August 1983, p. 242/248. The CCD memory is attractive for these and also other applications because of the very high information density due to the fact that per bit only one electrode is required. As compared with other memories, such as random access memories (RAM's), these CCD memories may be comparatively small with regard to the chip surface.
The aforementioned European Patent Application No. 0,099,931 discloses a CCD memory having a variable storage capacity, i.e. a memory in which the number of bits that can be stored is adjustable. The need for such a variable memory arises inter alia in the aforementioned television applications when the memory used must be suitable both for the 625 line system and for the 525 line system. With the use of a conventional CCD memory having a nonvariable capacity, the storage capacity will be adapted to the 625 lines system, which means that for the 525 lines system a number of lines of the memory will not contain useful information. With reference to FIGS. 14 and 15, EP-A 0,099,931 describes a 6-phase one-electrode/bit CCD, which, while maintaining the one-electrode/bit mode of operation, is shortened in that per group of six electrodes instead of the usual single site two empty sites are formed, as a result of which the storage capacity is reduced by a factor 4/5.
A disadvantage of the method described above is that the storage information traverses the memory at a two times higher speed because the empty sites are displaced simultaneously with respect to the embodiment shown in FIGS. 4-6, in which the maximum capacity of the memory is utilized. The frequency of the series registers therefore has to be doubled. Essentially, the storage time in this known device consequently is connected disproportionately with the storage capacity. Frequently, it is desirable to keep the clock frequency substantially constant both in the parallel section and in the series registers.